Efficient Implementation of Ogg Vorbis Decoder Using Soft Core Processor

Ogg Vorbis Bluespec Implementatin

An Efficient Viterbi Decoder Implementation for the ZSP500 DSP Core

This paper describes an efficient implementation of the Viterbi decoding algorithm on the ZSP500 digital signal processor (DSP) core. It starts with an introduction to convolutional coding and Viterbi decoding as a method of forward error correction in communication systems. An introduction to the ZSP500 architecture is followed by a description of special instructions for performing the Trelli...

Implementation of improved error trapping decoder for multiple error correcting cyclic codes in a soft core processor

This paper presents implementation of Tadao Kasami decoding algorithm for improved error trapping decoding and firmware realization details. Algorithm has been applied to cyclic (n, k) codes [Golay (23, 12) and BCH (31, 16)] for triple error correction. Microblaze 32-bit soft core processor was used with a Xilinx Spartan3 FPGA. To test decoder functionality, a test procedure with all possible e...

Efficient Implementation of XPath Processor on Multi-Core CPUs

Current XPath processors use direct approach to query evaluation which is quite inefficient in some cases and usually implemented serially. This may be a problem in case of processing complex queries on large documents. We propose algorithms and XML indexing techniques which are more efficient and which can utilize standard parallel templates. Our implementation is highly scalable and outperfor...

HDL Implementation of an Efficient Partial Parallel LDPC Decoder Using Soft Bit Flip Algorithm

Nowadays Low Density Parity Check Codes (LDPC) is more in demand in Wireless Communication Systems due to its excellent performance. Use of LDPC code for encoding and decoding purposes found to be more reliable and highly efficient data transfer over wide bandwidth in presence of corrupting noise. Various Algorithms were used to interpret LDPC codes. Out of which Sum Product Algorithm and Min S...